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HC
Junior Engineer for Korea ISG
hctz.fa.us2.oraclecloud.com · Seoul, Republic of, South Korea
About The Role
- Front-End Logic design
- Hardware design in Verilog HDL
- Verification with golden model
- Back-End design
- Logic synthesis / Formal verification
- Front-End Logic design
- Hardware design in Verilog HDL
- Verification with golden model
- Back-End design
- Logic synthesis / Formal verification
- -. Bachelor’s degree or above in Semiconductor-related or Electrical/Electronic Engineering
- -. Understanding of image sensors is preferred
- -. Proficiency in C++ and Python is preferred
- -. Strong English communication skills are preferred
- -. Meal and transportation expenses will be provided
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